The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band which will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or Gallium Arsenide (GaAs) technology to form the dice in these designs. Since WiGig transceivers use Digital to Analog Converters (DAC), the reduced power supply impacts the performance of the DAC's.
Complementary Metal Oxide Semiconductor (CMOS) is the primary technology used to construct integrated circuits. N-channel transistors and P-channel transistors (MOS transistor) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS transistors. Some of the current values for this technology include the channel length being 40 nm, the power supply of VDD equaling 1.2V and the number of layers of metal levels being 8 or more. This technology typically scales with technology.
CMOS technology delivers a designer the ability to form a very large system level design on one die which is known as a System On a Chip (SOC). The SOC is a complex system with millions, if not billions, of transistors which contain analog circuits and digital circuits. The analog circuits operate purely analog, the digital circuits operate purely digital and these two circuits types can be combined together to form circuits operating in a mixed-signal mode.
For example, digital circuits in their basic form only use digital logic and some examples can be a component comprising at least one; processor, memory, control logic, digital I/O circuit, reconfigurable logic and/or hardware programmed that to operate as hardware emulator. Analog circuits in their basic form use only analog circuits and some examples can be a component comprising at least one; amplifier, oscillator, mixer, and/or filter. Mixed signal in their basic form only use both digital and analog circuits and some examples can be a component comprising at least one: Digital to Analog Converter (DAC), Analog to Digital Converter (ADC), Programmable Gain Amplifier (PGA), Power Supply control, Phase Lock Loop (PLL), and/or transistor behavior control over Process, Voltage and Temperature (PVT). The combination of digital logic components with analog circuit components can appear to behave like mixed signal circuits; furthermore, the examples that have been provided are not exhaustive as one knowledgeable in the arts understands.
One of the critical design parameters of a transceiver occurs when a continuous analog signal is converted into a digital time signal in the ADC. A flash ADC uses a linear reference voltage source that is tapped and applied to one of the differential inputs of a number of parallel comparators. The input analog value is applied to the other differential input of all of the comparators simultaneously providing a very quick comparison. Several critical issues can occur in this conversion which includes: 1) the matching of the input transistors within and between the comparators; 2) clock kick-back from the clock enabling the comparators to the input signal; and 3) a reduction in bandwidth between the PGA and the large capacitive load of the ADC and the interconnect.
The matching of transistors within and between the comparators uses dummy transistors which use up valuable semiconductor area and causes an increase in the power dissipation due to increased wire lengths of the data and clock lines. If the matching of the transistors is not maintained well, the issue becomes a mismatching condition. The bandwidth of the ADC is limited by the input signal driving the input capacitive load of all the parallel comparators and the interconnect. This necessitates that the transistor width of the input transistors of the comparators to have an upper bound. Such a transistor width may not be sufficient and cause the matching problem to become more severe. Increasing the width of the transistor beyond this upper bound helps overcome the mismatching condition but causes the bandwidth of the ADC to reduce. Other solutions are required to resolve the mismatching condition yet allow the desired bandwidth to be satisfied simultaneously.
Clock kick-back from the clock to the input signal of a gate usually occurs via the capacitance coupling between the terminals of the active transistor, i.e., the gate overlap capacitance from the source and drain terminals to the gate terminal of an MOS transistor. As the width of the transistor is increased, the coupling capacitance increases which increases the clock kick-back. In addition, the power dissipation of the system increases as well because of the increased width of the transistors. A second aspect of clock kick-back is the transient behavior of the circuit being clocked between an initialization state and a steady state. The internal nodes of the clocked circuit during the transient period also generate a clock kick-back besides increasing the delay of the operation of the circuit. Several solutions are provided which overcome these shortcomings by reducing clock kick-back, thereby improving the performance of the circuit.
The signal delivery between the PGA and the ADC can be delayed by the large gate capacitance of the MOS transistors and the interconnect capacitance of the metal trace used to couple these comparators. The transfer of signals between the PGA and the ADC causes a decrease in the bandwidth of the path due to the capacitance. Typically, the performance of the ADC can be improved by increasing the width of the transistors to achieve a faster response. But the larger transistors, besides increasing the kick-back and power dissipation, also increase the delay of the signal delivery because of the larger gate capacitance being presented to the output of the PGA. The transfer of data on the interconnect between the PGA and ADC is critical to improving the performance of the system. A new technique will be presented to improve the signal's transfer at this critical node and improve the bandwidth of the captured signal.